Job Description

Role: Physical Design Engineer

Location: San Jose, CA

Open for FTE or C2C

Mandatory to look for the profiles with (Standard cells, Memories)

Description:

The role involves providing customization spec to vendors and PPA comparison of different foundation IP (memories, std cells, GPIO, eFUSE) used in next gen consumer SOC products. It also extends to resolving foundation IP issues and enabling our design teams for execution.

The candidate needs to:

• Work with arch, design & physical design teams to determine customizations for all foundation IP that are product differentiators
• Perform IP PPA analysis and vendor comparisons
• Provide specs and requirements to vendors
• Be able to understand and debug verilog, gls, dft, power management/upf modeling IP issues and communicate fixes to the team.
• Compile and create IP usage guidelines based on commonly encountered problems.
• Be data oriented, able to crunch through bug tracking system, and have front-end expertise

Be able to multitask and respond quickly to different teams

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

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• Dice Id: 91115415
• Position Id: 8398182

Job Tags

Contract work,

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